In the design of a VLSI semiconductor device, it is common to employ a delay stage to generate timing signals at various times. In some applications, it is desirable to use a delay stage that has minimum variations in its delay period as the voltage supply (such as V.sub.dd) changes. One such application is in the generation of sense amplifier timing signals of a dynamic random access memory (DRAM). At a low V.sub.dd level, all circuits tend to work slowly, and the sense amplifier clocks must fire quickly enough to meet storage cell restore time requirements. At a high voltage level, all circuits tend to draw more power supply current, and the sense amplifier clocks must work slowly enough to avoid exceeding peak current specifications.
Like other circuits, however, delay stages also tend to work slowly at low V.sub.dd levels and quickly at high V.sub.dd levels. If this delay variation is too large, an ordinary delay stage will be unable to satisfy the requirements at both extremes. A need has therefore arisen for a delay stage having reduced dependence in the length of its delay period on variations in the voltage supply level, or even a dependence in the opposite direction.